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Integrated Circuit Systems, Inc.
ICS9148-25
Pentium/ProTM System and CyrixTM Clock Chip
General Description
The ICS9148-25 is a Clock Synthesizer chip for Pentium and PentiumPro plus Cyrix CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU, seven PCI and eight SDRAM clocks. Two reference outputs are available equal to the crystal frequency, plus the IOAPIC output powered by VDDL. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50 5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9148-25 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V supply. Sperad Spectrum is modulated in center-spread mode on CPU/ SDRAM/PCI clocks. Modulation amount is selectable at power-up (latched inputs) for 0.5, 1.0, 2.0 or No spreading. * *
Features
* * * * * * * * * * Generates system clocks for CPU, IOAPIC, SDRAM, PCI, plus 14.318 MHz ), USB, Plus Super I/O Spread spectrum for CPU/SDRAM/PCI clocks default Supports single or dual processor systems Modulation of Spread Spectrum selectable as 0.5, 1.0, 2.0 or none Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3 and 68MHz (Turbo of 66.6) speeds. Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on PCI clocks CPU clocks to PCI clocks skew 1-4ns (CPU early) MODE input pin selects optional power management input control pins Two fixed outputs, 48MHz and 24 MHz Separate 2.5V and 3.3V supply pins - 2.5V or 3.3V output: CPU, IOAPIC (Strength selectable) - 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz No power supply sequence requirements 48 pin 300 mil SSOP
Pin Configuration
Block Diagram
48-Pin SSOP Power Groups
VDD = Supply for PLL core. VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:5) VDD3 = SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP# VDD4 = 48MHz, 24MHz VDDL1 = IOAPIC VDDL2 = CPUCLK (0:3)
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
Pentium is a trademark on Intel Corporation. 9148-25 Rev B 5/20/99
ICS9148-25
Pin Descriptions
PIN NUMBER 1 2 3, 10, 17, 24, 31, 37, 43 4 5 6 7,15 8 9 11, 12, 13, 14, 16 18 19 20 21 22 23 25 26 27 28,34 29, 30, 32, 33, 35, 36 38, 39, 41, 42 40 44 45 46 47 48 PIN NAME SSM1 REF1 REF0 GND X1 X2 MODE VDD2 PCICLK_F PCICLK0 SSM0 PCI_CLK (1:5) FS0 FS1 FS2 VDD4 48MHz 24MHz VDD SDRAM7 PCI_STOP# SDRAM6 CPU_STOP# VDD3 SDRAM (0:5) CPUCLK (0:3) VDD2 PD# IOAPIC VDDL1 CPU3.3_2.5# REF2 VDD1 TYPE IN OUT OU T PWR IN OUT IN PWR OUT OUT IN OUT IN IN IN PWR OUT OUT PWR OU T IN OUT IN PWR OUT OUT PWR IN OUT PWR IN OUT PWR DESCRIPTION Latched input for Spread Spectrum modulation amount (see table)* Reference clock output Reference clock output Ground (common) Crystal or reference input, nominally 14.318 MHz. Includes internal load cap to GND and feedback resistor from X2. Crystal output, includes internal load cap to GND. Input function selection for Power Management pins* Supply for PCICLK_F, and PCICLK (0:5) Free running PCI clock, not affected by PCI_STOP# PCI clocks Latched input for Spread Spectrum modulation amount (see table)* PCI clocks Frequency select 0 input* Frequency select 1 input* Frequency select 2 input* Supply for 48MHz and 24MHz clocks 48MHz driver output for USB clock 24MHz driver output for Super I/O Supply for PLL core SDRAM clock Halts PCI Bus (0:5) at next logic "0" level when low* SDRAM clock Halts CPU clocks at next logic "0" level when low* Supply for SDRAM (0:5), SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP SDRAMs clock at CPU speed CPUCLK clock output, powered by VDDL2 Supply for CPUCLK (0:3) Powers down chip, active low* IOAPIC clock output, powered by VDDL1, at crystal frequency Supply for IOAPIC Latched 3.3 or 2.5 VDD buffer strength selection* (see table) Reference clock output Supply for REF (0:2), X1, X2
*Internal pull-up resistor of 120 to 150K to 3.3V on indicated inputs.
Functionality
VDD = 3.3V 5% VDDL = 2.5V 5% or 3.3V 5%, TA = 0 to 70C Crystal (X1, X2) = 14.31818 MHz
FS2 0 0 0 0 1 1 1 1 FS 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPUCLK, SDRAM (MHz) 83.3 75 83.3 68.5 55 75 60 66.8 PCICLK (MHz) 1/2 CPU 30 (CPU/2.5) 33.3 (CPU/2.5) 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU 1/2 CPU
2
ICS9148-25
Mode Pin - Power Management Input Control
MODE, Pin 6 Pin 26 PCI_STOP# Input SDRAM7 Output Pin 27 CPU_STOP# Input SDRAM 6 Output
0
1
Power Management Functionality
CPU_STOP# PCI_STOP# PD# CPUCLK Outputs Stopped Low Stopped Low Stopped Low Running Running PCICLK(0:5) Outputs Stopped Low Stopped Low Running Stopped Low Running PCICLK_F, REF, 24/48MHz and SDRAM Stopped Low Running Running Running Running Crystal OSC Off Running Running Running Running VCO
X 0 0 1 1
X 0 1 0 1
0 1 1 1 1
Off Running Running Running Running
Spread Spectrum Functionality
Latched Pin 1 SSM1 0 0 1 1*
*default with internal pull-ups
Latched Pin 9 SSM0 0 1 0 1*
CPU, SDRAM and PCICLOCKS Normal, steady frequency mode Frequency modulated in center spread 2.0% Frequency modulated in center spread 1.0% Frequency modulated in center spread 0.5%
REF, IOAPIC 14.318MHz 14.318MHz 14.318MHz 14.318MHz
24MHz 24MHz 24MHz 24MHz 24MHz
48MHz 48MHz 48MHz 48MHz 48MHz
CPU 3.3_2.5V Buffer selector for CPUCLK and IOAPIC drivers.
CPU3.3_2.5# Latched Input Level 0 1 Buffer Selected for Operation at: 2.5V VDD 3.3V VDD
3
ICS9148-25
Technical Pin Function Descriptions
VDD(1,2,3,4) This is the power supply to the internal core logic of the device as well as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B and SDRAM(0:7). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. VDDL1,2 This is the power supplies for the CPUCLK and IOAPCI output buffers. The voltage level for these outputs may be 2.5 or 3.3volts. Clocks from the buffers that each supplies will have a voltage swing from Ground to this level. For the actual Guaranteed high and low voltage levels of these Clocks, please consult the DC parameter table in this Data Sheet. See control pin CPUCLK3.3_2.5# for output buffer strength matching VDDL required for skew control. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. X1 This input pin serves one of two functions. When the device is used with a Crystal, X1 acts as the input pin for the reference signal that comes from the discrete crystal. When the device is driven by an external clock signal, X1 is the device input pin for that reference clock. This pin also implements an internal Crystal loading capacitor that is connected to ground. See the data tables for the value of this capacitor. Also includes feedback resistor from X2. X2 This Output pin is used only when the device uses a Crystal as the reference frequency source. In this mode of operation, X2 is an output signal that drives (or excites) the discrete Crystal. The X2 pin will also implement an internal Crystal loading capacitor that is connected to ground. See the Data Sheet for the value of this capacitor. CPUCLK (0:3) These Output pins are the Clock Outputs that drive processor and other CPU related circuitry that requires clocks which are in tight skew tolerance with the CPU clock. The voltage swing of these Clocks are controlled by the Voltage level applied to the VDDL2 pin of the device. See the Functionality Table for a list of the specific frequencies that are available for these Clocks and the selection codes to produce them. See control pin CPUCLK3.3_2.5# for output buffer strength matching VDDL required for CPU to SDRAM skew control. These clocks are modulated by Sperad Spectrum. SDRAM(0:7) These Output Clocks are use to drive Dynamic RAM's and are low skew copies of the CPU Clocks. The voltage swing of the SDRAM's output is controlled by the supply voltage that is applied to VDD3 of the device, operates at 3.3 volts. These clocks are modulated by Sperad Spectrum. 48MHz This is a fixed frequency Clock output at 48MHz that is typically used to drive USB devices. 24MHz This pin is a fixed frequency clock output typically used to drive Super I/O devices. IOAPIC This Output is a fixed frequency Output Clock that runs at the Reference Input (typically 14.31818MHz) . Its voltage level swing is controlled by VDDL1 and may operate at 2.5 or 3.3volts. REF(0:2) The REF Outputs are fixed frequency Clocks that run at the same frequency as the Input Reference Clock X1 or the Crystal (typically 14.31818MHz) attached across X1 and X2. PCICLK_F This Output is equal to PCICLK(0:5) and is FREE RUNNING, and will not be stopped by PCI_STP#. This clock is modulated by Spread Spectrum. PCICLK (0:5) These Output Clocks generate all the PCI timing requirements for a Pentium/Pro based system. They conform to the current PCI specification. They run at 1/2 CPU frequency, or CPU/2.5, see frequency table. These clocks are modulated by Sperad Spectrum. FS (0,1,2) These Input pins control the frequency of the Clocks at the CPU, PCICLK and SDRAM output pins. See frequency table. These pins are all Full-time inputs with a pull-up to VDD. MODE This Input pin is used to select the Input function of the Power Management I/O pins 26 and 27. An active Low will place pins in the Input mode and enable those stop clock functions. This pin is a full-time input with a pull-up to VDD.
4
ICS9148-25
Technical Pin Function Descriptions
CPU3.3_2.5# This Input pin controls the CPU and IOAPIC output buffer strength for skew matching CPU and SDRAM outputs to compensate for the external VDDL supply condition. It is important to use this function when selecting power supply requirements for VDDL1,2. A logic "0" (ground) will indicate 2.5V operation and a logic "1" will indicate 3.3V operation. This pin has an internal pull-up to VDD. This pin is a latched input. PD# This is an asynchronous active Low Input pin used to Power Down the device into a Low Power state by not removing the power supply. The internal Clocks are disabled and the VCO and Crystal are stopped. Powered Down will also place all the Outputs in a low state at the end of their current cycle. The latency of Power Down will not be greater than 3ms. This pin is a Full-time input with a pull-up to VDD. CPU_STOP# This is a active Low Input pin used to stop the CPUCLK clocks in an active low state. All other clocks will continue to run while this function is enabled. The CPUCLK's will have a turn OFF latency and a turn ON latency of 2 or 3 CPU clocks. This pin is a Full-time input with a pull-up to VDD. PCI_STOP# This is a synchronous active Low Input pin used to stop the PCICLK (0:5) clocks in a low state. It will not effect PCICLK_F or any other outputs. There is only one full PCI clock output for Turn OFF or Turn ON latency. This pin is a Full-time input with a pull-up to VDD. SSM (0:1) These pins define the input condition for the Spread Spectrum amount of modulation. See Spread Spectrum functionality table. Note that spreading is only done on the CPU/SDRAM/ PCI clocks no modulation is done on the REF, IOAPIC or PLL2 (24, 48MHz) outputs. These latched input pins are defined at power-on for logic Hi or logic Low condition by external pull-up or pull-down resistors, or the internal pull-up resistor to VDD. See shared pin operation of Input/output pins on next page.
5
ICS9148-25
Shared Pin Operation Input/Output Pins
Pins 1, 9 & 47 on the ICS9148-25 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. There is no degradation to the output clocks from resistors as low as 2K ohm. The internal pull-up resistors can be used as the logic high program input. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device's internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s).
Fig. 1
6
ICS9148-25
Fig. 2a
Fig. 2b
7
ICS9148-25
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance Transition Time Settling Time
1 1 1 1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi CIN CINX Ttrans Ts
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq.
0.1 2.0 -100 75 8 14.318
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 95 600 mA A MHz 5 45 3 pF pF ms ms 3 500 4.5 ms ps ns ps
27
36 5 200
Clk Stabilization Skew
1 1
TSTAB From VDD = 3.3 V to 1% target Freq. TCPU-SDRAM1 VT = 1.5 V TCPU-PCI1 VT = 1.5 V; TREF-IOAPIC VT = 1.5 V; 1
2 900
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew
1 1
SYMBOL IDD2.5OP
CONDITIONS CL = 0 pF; Select @ 66M
MIN
TYP 8 250
MAX 9.5 500 4
UNITS mA ps ps ns
TCPU-SDRAM2 VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TREF-IOAPIC VT = 1.5 V; VTL = 1.25 V; SDRAM Leads TCPU-PCI2 VT = 1.5 V; VTL = 1.25 V; CPU Leads 1
260 2
Guarenteed by design, not 100% tested in production.
8
ICS9148-25
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -13.0 mA IOL = 14 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 10 10 2
TYP
MAX UNITS 25 25 V V mA mA ns ns ns ps ps ps ps
RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B
1 1 1 1
22
2.2 0.3 -25 26 1.35 1.2
0.4 -16 1.6 1.6 55 250 250 150 +250
dt2B
45
50 60 150 30
tsk2B
tjcyc-cyc2B tj1s2B
1 1
1
VT = 1.25 V VT = 1.25 V VT = 1.25 V -250
tjabs2B
80
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1
1 1 1 1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 12 2.6
TYP
MAX UNITS 55 55 V V mA mA ns ns % ps ps ps
40
3.1 0.15 -62 55 1.5 1.4
0.4 -40 2 2 60 500 150 250
dt1
45
50 200 10
tsk1
tj1s1 tjabs11
-250
65
Guarenteed by design, not 100% tested in production.
9
ICS9148-25
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.6
TYP
MAX UNITS 24 24 V V mA mA ns ns % ps ps ps
RDSN3 VOH3 VOL3 IOH3 IOL3 Tr3 Tf3 Dt3
1 1 1 1
40
2.8 0.3 -62 55 1.5 1.4
0.4 -40 2 2 60 500 150 250
45
50 200 50
Tsk3
Tj1s3
1 1
Tjabs3
-250
100
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP4B
1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V
MIN 10 10 2
TYP
MAX UNITS 30 30 V V mA mA ns ns % ps 400 1000 ps ps
RDSN4B VOH4\B VOL4B IOH4B IOL4B tr4B tf4B
1 1 1
19
2.5 0.3 -25 23 1.4 1.2
0.5 -16 1.6 1.6 60
dt4B
40
53 1400 300
tjcyc-cyc4B tj1s4B
1 1
1
VT = 1.25 V VT = 1.25 V VT = 1.25 V -1000
tjabs4B
800
Guarenteed by design, not 100% tested in production.
10
ICS9148-25
Electrical Characteristics-REF1, 48MHz, & 24MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP7 RDSN7 VOH7 VOL7 IOH7 IOL7 Tr7 Tf7 Dt7
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.6
TYP
40
2.75 0.3 -62 50 1.4 1.4
MAX UNITS 24 24 V 0.4 V -40 mA mA 2 2 55 400 1000 ns ns % ps ps ps
45
54 1400 210
tjcyc-cyc7 Tj1s7
1 1
Tjabs7
-1000
450
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF0
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 45 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP7 RDSN7 VOH7 VOL7 IOH7 IOL7 Tr7 Tf7 Dt7
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.6
TYP
41
2.75 0.3 -62 50 1.8 1.8
MAX UNITS 24 24 V 0.4 V -54 mA mA 2.2 2.2 60 400 1000 ns ns % ps ps ps
40
54 1400 350
tjcyc-cyc7 Tj1s7 Tjabs71
1
-1000
900
Guarenteed by design, not 100% tested in production.
11
ICS9148-25
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended. Connections to VDD:
12
ICS9148-25
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100 VARIATIONS AC AD MIN. .620 .720 D NOM. .625 .725 N MAX. .630 .730 48 56
X
This table in inches
Ordering Information
ICS9148F-25
Example:
ICS XXXX F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
13

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